1. Field of the Invention
The present invention relates to a nonvolatile semiconductor device, particularly, for write/erase control of a flash EEPROM.
2. Description of the Related Art
FIG. 15 shows a cross-sectional view of a memory transistor in a flash EEPROM. Data is written in the memory transistor by simultaneously applying a high voltage to a control gate electrode 17 and drain region 15 while setting a source region 14 at GND level. Such a setting will cause a voltage sufficient to create an avalanche breakdown to be applied between the drain region 15 and a substrate 21. Since the high voltage is also applied to the control gate electrode 17, only hot electrons in hot carriers produced by the avalanche breakdown are selectively injected into a floating gate electrode 16. Thus, the threshold voltage in the memory transistor as viewed from the control gate electrode 17 increases to permit the write of data.
Data can be erased by setting the control gate electrode at GND level and the drain region 15 at Open level (or GND level) and also by applying the high voltage to the source region 14. In other words, when the high voltage is applied to the source region 14, electrons in the floating gate electrode 16 tunnel a thin gate oxide film 19 between the source region 14 and the floating gate electrode 16. Thus, the electrons are drawn from the floating gate electrode 16 into the source region 14. As a result, the threshold voltage of the memory transistor as viewed From the control gate electrode 17 will decrease to permit tile erase of data.
FIG. 16 shows a circuit diagram of a nonvolatile semiconductor device constructed in accordance with the prior art. The nonvolatile semiconductor device of FIG. 16 is shown to be of four-transistor type for simplification.
The write operation will first be described. When the write is to be made in a memory transistor 1a, node a and b and the output Y1 of a Y-selector 803 arc set at H level (upper logical inversion level); a node c and the output Y2 of the Y-selector 803 are set at L level (lower logical inversion level); the output WL1 of an X-decoder 802 is set at high-voltage Vpp level and the output WL2 of the X-decoder 802 is set at GND level. Furthermore, a write control circuit 804 is set to output the Vpp level. Thus, transistors 40, 42 and 48 are turned on and transistors 29, 44 and 46 are turned off. BL1 and WL1 are set at Vpp level; BL2 is set at Open level; and WL2 and SL are set at GND level. By such a setting, the potential of the memory transistor 1a at its drain region and control gate electrode will only be Vpp level. As a result, only the memory transistor 1a generates hot electrons at the drain region end so that the electrons will be injected into the floating gate electrode to permit the write operation. In such a case, the other memory transistors 1b, 1c and 1d will not make the writing operation since no channel current is produced therein.
The erase operation will be then described. The node a is set at L level; the outputs Y1 and Y2 of the Y-selector 803 are set at L level; and the outputs WL1 and WL2 of the X-decoder 802 are set at GND level. When an erase pulse is applied to the node c under such a condition, the pulse signal is inputted into a transistor 29 through an inverter 32 and interface circuit 34. As a result, the transistor 29 is turned on and a source line SL becomes Vpp level. In the memory transistors 1a-1d, thus, BL1 and BL2 are set at Open level; WL1 and WL2 are set at GND level; and SL is set at Vpp level. A tunnel current is then produced between the floating gate electrode and the source region. As a result, electrons are released from the floating gate electrode to the source region. The erasure will be thus made in the memory transistors 1a-1d.
Data can be read out by setting the node b at L level and also by detecting the potential of the bit line BL1 or BL2 through a sense amplifier 822.
If the electrons are too much drawn from the floating gate electrode 16 into the source region 14 in the above erasure, however, the threshold voltage in the memory transistors will be negative. Such a phenomenon is known as "overerasing". In the overerasing, the read-out or data generates a leak current in the memory transistors so that they will not properly be operated. In order to prevent the overerasing, a technique known as "verify" may be used. In the verify operation, the threshold voltage or a memory transistor to be erased is monitored to judge whether or not the threshold voltage is in a given proper range after the erase operation. Such judgment is accomplished by comparing the threshold voltage of the memory transistor to be erased with a predetermined reference voltage (which will be called "verify voltage"). More particularly, if the threshold voltages of all the memory transistors to be erased are equal to or lower than the verify voltage, it is judged that the erasure for the memory transistors has been properly performed. The subsequent erasure is ceased. On the other hand, even if tile threshold voltage in only one of the memory transistors to be erased is higher than the verify voltage, it is judged that the erasure has not properly been made. The erasing operation is again performed before the verifying operation is again carried out. Such a procedure will be repeated until all the memory transistors have been erased properly.
If the threshold voltages in all the memory transistors are equal to or lower than the verify voltage, the subsequent erasure will be ceased. Therefore, an overerasing may probably be created in a faster erase speed memory transistor, that is, a memory transistor that its threshold voltage is more largely shifted to the negative direction in the erase operation.
The verify technique of the prior art can make the erasure only with the same erasing voltage and only through the same erasing time period. In order to prevent the overerasing, the erasing voltage can be reduced with the erasing time period to decrease the shift of the threshold voltage in the memory transistor to the negative direction. If the shift of the threshold voltage to the negative direction is too much reduced, the erasing operation will undesirably require more time. On the contrary, if the erasing voltage is increased with increase of the erasing time period to increase the speed of erasure, the possibility of overerasing will be highly increased. Therefore, the erasing voltage and time period must properly be controlled. A technique of controlling the erasing voltage is disclosed as by Japanese Patent Laid-Open No. Hei 2-123597. Such a technique can satisfactorily prevent the characteristics of a memory transistor to be degraded by repetition of the write/erase, but not overcome the above problem of overerasing in the verify and other operations. The prior art does not comprise any means for preventing the overerasing in the verify and other operations. Another technique of control the erasing time period is disclosed as by Japanese Patent Laid-Open No. Hei 2-5296. The object of this technique is also to prevent the characteristics of a memory transistor from being degraded by repetition of the write/erase. The erasure time control process provided by Japanese Patent Laid-Open No. Hei 2-5296 is adapted to limit the erasing time period through the provision of a timer circuit and not suitable for use in prevention of the overerasing.